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RM0008
16-bit NAND Flash
Table 115. 16-bit NAND Flash
Flexible static memory controller (FSMC)
FSMC signal name
A[17]
A[16]
D[15:0]
NCE[x]
NOE(= NRE)
NWE
NWAIT/INT[3:2]
I/O
O
O
I/O
O
O
O
I
Function
NAND Flash address latch enable (ALE) signal
NAND Flash command latch enable (CLE) signal
16-bit multiplexed, bidirectional address/data bus
Chip select, x = 2, 3
Output enable (memory signal name: read enable, NRE)
Write enable
NAND Flash ready/busy input signal to the FSMC
There is no theoretical capacity limitation as the FSMC can manage as many address
cycles as needed.
Table 116. 16-bit PC Card
FSMC signal name
A[10:0]
NIOS16
NIORD
NIOWR
NREG
D[15:0]
NCE4_1
NCE4_2
NOE
NWE
NWAIT
INTR
CD
I/O
O
I
O
O
O
I/O
O
O
O
O
I
I
I
Function
Address bus
Data transfer width in I/O space (16-bit transfer only)
Output enable for I/O space
Write enable for I/O space
Register signal indicating if access is in Common or Attribute space
Bidirectional databus
Chip select 1
Chip select 2 (indicates if access is 16-bit or 8-bit)
Output enable
Write enable
PC Card wait input signal to the FSMC (memory signal name
IORDY)
PC Card interrupt to the FSMC (only for PC Cards that can generate
an interrupt)
PC Card presence detection
Doc ID 13902 Rev 9
443/995
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